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| PS6500 6.5 GHz Fractional-N Frequency Synthesizer Low-Power Direct Digital Modulation Frequency Synthesizer Preliminary Datasheet V1.1 Features * 6.5 GHz operating frequency * Small step size 400 Hz or less * High internal reference frequency, up to 25 MHz, enables larger loop bandwidth PLL * Very fast switching speed (for example, 100 s with 25 MHz reference frequency) * Low phase noise floor (for example, -80 dBc/Hz in loop bandwidth) * Low spurious power (-70 dBc) in loop bandwidth * Software programmable power-down modes * Delta-Sigma Fractional-N main and auxiliary synthesizers * High speed serial interface up to 100 Mbps * 3 wire programming * Programmable division ratios on reference frequency * Phase detectors with programmable gains to provide a programmable loop bandwidth * Frequency Power SteeringTM speeds up acquisition 5x with same loop filter * On-chip crystal oscillator * Supports frequency adjust for temperature compensation and automatic frequency control (AFC) * Direct digital modulation * 3 volt analog and digital operation * 5 volt tolerant on digital pins * Up to 5 volt output to loop filter * 28-pin EP-TSSOP package Product Description The PS6500 Direct Digital Modulation Fractional-N frequency synthesizer provides ultra-fine frequency resolution, fast switching speed, and low phase-noise performance. This synthesizer is a key building block in designing high-performance narrowband and multi-band radio systems that require low power and fine step size. The ultra-fine step size of less than 400 Hz allows this synthesizer to be used in very narrowband wireless applications. With proper temperature sensing or through control channels, the synthesizer's fine step size can compensate for crystal oscillator or IF filter drift. As a result, crystal oscillators or crystals can replace temperature-compensated or ovenized crystal oscillators, reducing parts count and associated component cost. The PS6500's fine step size can also be used for doppler shift corrections. The PS6500 has a phase noise floor of -80 dBc/Hz up to 6.5 GHz operation. This is permitted by the on-chip low noise prescalers and low divide ratios provided by the IC's high fractionality. Reference crystals or oscillators up to 50 MHz can be used with the PS6500. The crystal frequency is divided down by independent programmable dividers (1 to 32) for the main and auxiliary synthesizers. The phase detectors can operate at a maximum speed of 25 MHz, permitting better phase noise due to the lower division value. With a high reference frequency, the loop bandwidths can also be increased. Larger loop bandwidths improve the settling times and reduce in-band phase noise. Typical switching times of less than 100 s can thus be achieved with a 10 MHz reference. The PS6500's lower in-band phase noise also permits the use of lower cost Voltage Controlled Oscillators (VCOs) in customer applications. The PS6500 has a Frequency Power SteeringTM circuit (patent pending), that assists the loop filter to steer the VCO when the frequency is too fast or too slow. In this configuration, acquisition times of up to five times faster than conventional phase/frequency detectors can be achieved. The unit operates with a 3-wire, high-speed serial interface. A combination of a large bandwidth, fine resolution, and the 3-wire, high-speed serial interface allows for a direct phase and frequency modulation of the VCO. This supports any constant envelope and continuous phase modulation which means any analog FM or digital FM. This capability can eliminate the need for I & Q DACs, quadrature upconverters, and IF filters from the transmitter portion of the radio system.1 Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 -1- Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Benefits The Philsar PS6500 provides has the following benefits: * Small step size allows for higher internal reference frequency which permits a lower multiplication ratio improving phase noise. * Lower phase noise permits the use of a wider loop filter bandwidth, which in turn yields a faster frequency switching and acquisition time. * Small step size allows flexibility in choosing a reference crystal or oscillator frequency, as very narrow channel spacing can be supported. * The on-chip oscillator permits use of a crystal instead of a crystal oscillator lowering the system cost. * Programmable phase detector gain allows for variable loop filer bandwidths. Frequency switching and acquisition times can be improved by opening up the bandwidth, and subsequently lower phase noise contribution can be achieved by narrowing down the loop filter bandwidth after phase lock. * Programmable power-down modes optimize power management. * Individually configurable main and auxiliary synthesizers as integer-N, allowing a reduction in power consumption. * Configurable resolution of the main modulator from 18 to 10 bits, allowing further reduction in power consumption. Note that there are 16 to 8 bits of effective resolution as 2 bits are lost to a front-end divide-by-4 before the multi-modulus prescaler. Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 -2- Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Figure 1: PS6500 Block Diagram Data Clock /CS Serial Interface Modul. data Main Main Div. Registers Modul. Ctl Ref. Div Synth Ctl Aux. Div. Aux. Mod_in Modulation Unit Mux Mux_out 18-bit 10-bit Fractional Unit Reference Frequency Dividers Fractional Unit Fvco_main /Fvco_main Divide-by-4 Prescaler Main Prescaler Main Divider Fref_main Fpd_main Main Phase/Freq. Detector and Charge Pump Fref Fref_aux Fpd_aux Auxiliary Phase/Freq. Detector and Charge Pump Auxiliary Divider Auxiliary Prescaler Fvco_aux /F vco_aux Reference Frequency Oscillator PDout_main PDout_aux LD/PSaux Lock Detection or Power Steering LD/PS main Lock Detection or Power Steering Product Description Serial Interface The serial interface is a versatile 3-wire interface, Clock (serial clock), Data (serial input) and /CS (chip select). It enables the PS6500 to operate in a system where one or multiple masters and slaves are present. To perform a loop-back test at start-up and to check the integrity of the board and processor, the serial data can be fed back to the master device (for example, MCU/MPU) through a programmable multiplexer. This facilitates hardware and software debugging. For more information, see "Serial Interface" on page 5. Registers There are ten 16-bit registers in the PS6500. For more information, see "Registers" on page 19 and "Register Descriptions" on page 19. Main and Auxiliary Modulators The PS6500 uses a proprietary (patent pending) configurable 10-bit or 18-bit modulator for the main synthesizer and 10-bit modulator for the auxiliary synthesizer to provide fractionality. Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 -3- Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Main and Auxiliary Fractional Units The PS6500 provides fractionality through the use of main and auxiliary modulators. The output from the main and auxiliary modulators are combined with the main and auxiliary divider ratios through their respective Fractional Units. VCO Prescalers The VCO prescalers provide low-noise signal conditioning of the VCO signals. They are used to translate from an off-chip single-ended or differential signal to an on-chip differential ECL/CML signal. The PS6500 has independent main and auxiliary VCO prescalers. Main and Auxiliary VCO Dividers The PS6500 provides programmable dividers that control the ECL/CML prescalers and supply the required signals to the charge pump phase detectors. Programmable divide ratios ranging from 152 to 2148 are possible in fractional-N mode, and from 128 to 2172 in integer-N mode. Note that due to the fixed Divide-by-four divider on the main synthesizer, the divide ratios are multiples of four. Programmable divide ratios ranging from 38 to 537 are possible in fractional-N mode, and from 32 to 543 in integer-N mode for the auxiliary synthesizer. Reference Frequency Oscillator The PS6500 has a self-contained low-noise crystal oscillator. This crystal oscillator is followed by the clock generation circuitry that generates the required clock for the programmable reference frequency dividers. Reference Frequency Dividers The crystal oscillator signal can be divided by a ratio of 1 to 32 to create the reference frequencies for the phase detectors. The PS6500 has both a Main and an Auxiliary frequency synthesizer and provides independently configurable dividers of the crystal oscillator frequency for both the main and auxiliary phase detectors. The divide ratios can be programmed through the Reference Frequency Dividers Register. Note: The divided crystal oscillator frequencies (which are the internal reference frequencies) Fref_main and Fref_aux are referred to as the reference frequencies throughout this document. Phase Detectors and Charge Pumps The PS6500 uses a separate charge pump phase detector (patent pending), for each synthesizer which provides a programmable gain, Kd, from 8 to 80 A/radian in steps of 2.25 A/radian. Phase detector gains are programmable through the control register. Frequency Steering When programmed for Power SteeringTM (patent pending), the PS6500 has a frequency power steering circuit, which assists the loop filter to steer the VCO, through the LD/PS pin. In this configuration, the LD/PS pin can provide for more rapid acquisition (approximately five times faster than conventional phase/frequency detectors). When programmed for lock detection, internal frequency steering is implemented and provides frequency acquisition times comparable to conventional phase/frequency detector. Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 -4- Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Lock Detection When programmed for lock detection, the PS6500 provides on the LD/PS pin, an active low pulsing open collector output to indicate the out-of-lock condition. When locked, the LD/PS pin is tri-stated (high impedance). Power Down The PS6500 supports a number of power-down modes through its serial interface. For more information, see "General Synthesizer Registers" on page 22. Operation This section describes the operation of the PS6500. The serial interface is described first, followed by information on how to obtain values for the divide ratio registers. Serial Interface The serial interface of the PS6500 consists of three pins: Clock, Data and /CS. Data transfers are controlled by the Clock signal which synchronizes and samples the information on the two serial data lines (Data and /CS). The bits on the Data pin are shifted into a temporary register on the rising edge of Clock. The /CS (chip select) line allows individual selection of slave devices on the same bus. The following diagram functionally depicts how a serial transfer takes place. Figure 2: Serial Transfer Timing Diagram Clock Data /CS Last A serial transfer is initiated when a microcontroller or microprocessor forces the /CS line to a low state. This is immediately followed by an address/data stream being presented to the Data pin that coincides with the rising edges of the clock presented on the Clk line. Each rising edge of the Clk signal shifts in one bit of data on the Data line into the shift-register. At the same time, one bit of data is being shifted out for the Mux_out pin (if the serial bit stream is selected) at each falling edge of Clk. To load any of the synthesizer registers, 16 bits of address/data have to be presented to the Data line with the data LSB last while /CS is low. If /CS is low for more than 16 clock cycles, only the last address/data bits are used for loading the synthesizer registers. If the /CS line is brought to a high state before the thirteenth clock edge on Clk, the bit stream is assumed to be modulation data samples. In this case, it is assumed that no address bits are present and that all the bits in the stream should be loaded into the modulation data register X A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXX Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 -5- Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Synthesizer Register Programming In the following equations, Nfractional Desired VCO division ratio in fractional-N applications. This number is a real number and can be interpreted as the reference frequency (Fref) multiplying factor such that the resulting frequency is equal to the desired VCO frequency. Desired VCO division ratio in integer-N applications. This number is an integer and can be interpreted as the reference frequency (Fref) multiplying factor such that the resulting frequency is equal to the desired VCO frequency. 9-bit unsigned input value to the divider ranging from 0 to 511(Integer-N mode) and from 6 to 505 (Fractional-N mode) 262144 when the modulator is in 18-bit mode, 1024 when the is in 10-bit mode When in 18-bit mode, 18-bit signed input value to the modulator, ranging from -131072 to +131071 providing 262144 steps, each of Fdiv_ref / 218 (Hz). or when in 10-bit mode, 10-bit signed input value to the modulator, ranging from -512 to +511 providing 1024 steps, each of Fdiv_ref / 210 Hz. Desired VCO frequency (either Fvco_main or Fvco_aux). Divided reference frequency presented to the phase detector (either Fref_main or Fref_aux). Ninteger Nreg divider dividend FVCO Fdiv_ref Fractional-N Applications The desired division ratio is for the Main Synthesizer is given by: N fractional = FVCO_main / (4 x Fdiv_ref) The desired division ratio is for the Auxiliary Synthesizer is given by: N fractional = FVCO_aux / Fdiv_ref where Nfractional must be between 150 and 2150 for the main synthesizer or between 37.5 and 537.5 for the auxiliary. The value to be programmed in the Main or Auxiliary Divider Register is given by: N reg = Round 1 [Nfractional] - 32 When in fractional mode, allowed values for Nreg are from 6 to 505 inclusive. The value to be programmed in the Main or Auxiliary Dividend Register(s) is given by: dividend = Round [divider x (Nfractional - Nreg - 32)] 1. Where the Round function rounds the number to the nearest integer. Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 -6- Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer where the divider is either 1024 in 10-bit mode or 262144 in 18-bit mode. Therefore, the dividend is a signed binary value either 10 or 18 bits long. Note: Because of the high fractionality of the Direct Digital Modulation Fractional-N Frequency Synthesizer, there is no practical need for any integer relationship between the reference frequency and the channel spacing or desired VCO frequencies. Fractional-N Example Case 1: To achieve a desired frequency FVCO_main of 5900.4530 MHz using crystal frequency of 40 MHz with operation of the synthesizer in 18-bit mode. Since the maximum internal reference frequency Fdiv_ref is 25 MHz, the crystal frequency is divided by 2 to obtain a Fdiv_ref of 20 MHz 1. Therefore, using: N fractional = FVCO / (4 x F div_ref) = 5900.4530 / 80 = 73.7557 The value to be programmed in the Main Divider Register is: N reg = Round [Nfractional] - 32 = Round[73.7557] - 32 = 74 - 32 = 42 = 0 0010 1010(binary) With the modulator in 18-bit mode, the value to be programmed in the Main Dividend Registers is dividend = Round (divider x (N fractional - Nreg - 32)) = Round (262144 x (73.7557 - 42 - 32)) = Round (262144 x (-0.2443375)) = Round (-64051.6096) = -64052 (decimal) = 11 0000 0101 1100 1100 (binary) Where 11 0000 0101 is loaded in the Main Dividend MSB Register and 1100 1100 is loaded in the Main Dividend LSB Register. 1. The frequency step size for this case is 4 x 20 MHz divided by 2 18 giving 305.2 Hz. Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 -7- Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Summarizing, * Main Divider Register = 0 0010 1010 * Main Dividend LSB Register = 1100 1100 * Main Dividend MSB Register = 11 0000 0101 * The resulting main VCO frequency is 5900.4529 * Step size is 305 Hz Case 2: Assuming a desired frequency FVCO_main of 5217.1776 MHz and a crystal frequency of 19.2 MHz with operation of the synthesizer in 10-bit mode. Since the maximum internal reference frequency Fdiv_ref is 25 MHz, the crystal frequency does not require the internal division to be greater than 1, giving us a Fdiv_ref of 19.2 MHz 1. Therefore, using: N fractional = FVCO_main / (4 x Fdiv_ref) = 5217.1776 / 4 x 19.2 = 67.9320 The value to be programmed in the Main Divider Register is: N reg = Round [Nfractional] - 32 = Round [67.9320] - 32 = 68 - 32 = 36 = 0 0010 0100 (binary) With the modulator in 10-bit mode, the value to be programmed in the Main Dividend Registers is: dividend = Round (divider x (N fractional - Nreg - 32)) = Round (1024 x (67.9320 - 36 - 32)) = Round (1024 x (-0.068)) = Round (-69.632) = -70 (decimal) = 11 1011 1010 (binary) Where 11 1011 1010 is loaded in the Main Dividend MSB Register. 1. The frequency step size for this case is 4 x 19.2 MHz divided by 210 giving 75 kHz. Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 -8- Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Summarizing, * Main Divider Register = 0 0010 0100 * Main Dividend MSB Register =11 1011 1010 * The resulting VCO frequency is 5217.15 MHz * Step size is 75 kHz Integer-N Applications The desired division ratio for the Main or Auxiliary Synthesizer is given by: N integer = FVCO_main / Fdiv_ref where Ninteger is an integer number from 32 and 543 for both the main and auxiliary synthesizers. The value to be programmed in the Main or Auxiliary Divider Register is given by: N reg = Ninteger - 32 When in integer mode, allowed values for Nreg are from 0 and 511 for both the main and auxiliary synthesizers. Note: As with all integer-N synthesizers, the minimum step size is related to the crystal frequency and reference frequency division ratio. Integer-N Example Case 1: To achieve a desired frequency FVCO_aux of 400 MHz using a crystal frequency of 16 MHz. Since the minimum divide ratio is 32, the reference frequency must be a maximum of 12.5 MHz. Choosing a reference frequency divide ratio of 2 provides us with a reference frequency Fdiv_ref of 8 MHz. Therefore, using: N integer = FVCO_aux / Fdiv_ref = 400 / 8 = 50 The value to be programmed in the Auxiliary Divider Register is: N reg = Ninteger - 32 = 50 - 32 = 18 = 0 0001 0010 (binary) Summarizing, * Auxiliary Divider Register = 0 0001 0010 Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 -9- Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Register Loading Order In applications where the main synthesizer is in 18-bit mode, the Main Dividend MSB Register holds the 10 MSBs of the dividend and the Main Dividend LSB Register holds the 8 LSBs of the dividend. The order in which the registers controlling the main synthesizer's divide ratio are to be loaded is: * Main Divider Register * Main Dividend LSB Register * Main Dividend MSB Register (at which point the new divide ratio takes effect). In applications where the main synthesizer is in 10-bit mode, the Main Dividend MSB Register holds the 10 bits of the dividend. The order in which the registers controlling the main synthesizer's divide ratio are to be loaded is: * Main Divider Register * Main Dividend MSB Register (at which point the new divide ratio takes effect). For the auxiliary synthesizer, the Auxiliary Dividend Register holds the 10 bits of the dividend. The order in which the registers controlling the auxiliary synthesizer's divide ratio is to be loaded is: * Auxiliary Divider Register * Auxiliary Dividend Register (at which point the new divide ratio takes effect). Note: When in integer mode, the new divide ratios take effect as soon as the Main or Auxiliary Divider Register is loaded. Direct Digital Modulation The PS6500's high fractionality and small step size permit the user to tune to practically any frequency in the VCO's operating range. This frequency tuning permits direct digital modulation by programming the different desired frequencies at precise instants. Typically, the channel frequency is selected through the main divider and dividend register and the instantaneous frequency offset from the carrier is entered through the modulation data register. Write access to the modulation data register can be performed three ways: Normal register write A normal 16-bit serial interface write to the modulation data register at address Hex9 where /CS is 16 Clock cycles wide and modulation data is presented on the Data pin. The content of the modulation data register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (Fpd_main). Short /CS through Data pin (no address bits required) Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 10 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer A shortened serial interface write where /CS is from 2 to 12 Clock cycles wide and modulation data (2 to 12 bits) is presented on the Data pin. The Data is the default pin for entering modulation data directly in modulation data register with shortened /CS strobes. This method of data entry eliminates the register address overhead on the serial interface. All serial interface bits are re-synchronized internally at the reference oscillator frequency. The content of the modulation data register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (Fpd_main). Short /CS through Mod_in pin (no address bits required) A shortened serial interface write where /CS is from 2 to 12 Clock cycles wide and modulation data (2 to 12 bits) is presented on the Mod_in pin. The Mod_in is the alternate pin for entering modulation data directly in modulation data register with shortened /CS strobes. This mode is selected through the modulation control register. This method of data entry also eliminates the register address overhead on the serial interface and permits a different device than the one controlling the channel selection to enter the modulation data (eg. a microcontroller for channel selection and a DSP for modulation data). All serial interface bits are re-synchronized internally at the reference oscillator frequency and the content of the modulation data register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (Fpd_main). Modulation data samples in the modulation data register can be from 2 to 12 bits long, enabling the user to select how many distinct frequency steps will be used for the desired modulation scheme. The user can also control the frequency deviation through the Modulation Data Magnitude Offset in the modulation control register. This permits shifting of the modulation data to accomplish a 2m multiplication of frequency deviation1. 1. The programmable range of -0.5 to +0.5 of the main modulator can be exceeded up to the condition where the sum of the dividend and the modulation data obey -0.5625 (Nmod + dividend) +0.5625 before requiring changing Ninteger Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 11 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Figure 3: PS6500 Pinout Clock Mod_in Mux_out VSUBdigital GNDecl/cml VCCecl/cml Fvco_main /Fvco_main LD/PSmain VCCcp_main CPout_main GNDcp_main Xtalacgnd/Osc Xtalin/Osc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 /CS Data VCCdigital GNDdigital VCCecl/cml Fvco_aux /Fvco_aux GNDcp_aux CPout_aux VCCcp_aux LD/PSaux GNDxtal VCCxtal Xtalout/NC Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 12 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Table 1: PS1200 Pin Description Pin Label Clock Pin # Pin 1 Type Digital input Description Clock signal pin. When /CS is low, the register address and data is shifted in address bits first on the Data pin on the rising edge of Clock. For more information, see "Serial Interface" on page 5. Serial address and data input pin. Address bits are followed by data bits. For more information, see "Serial Interface" on page 5. Active low enable pin. Enables loading of address and data on the Data pin on the rising edge of Clock. When /CS goes high, data is transferred to the register indicated by the address. Subsequent clock edges are ignored. For more information, see "Serial Interface" on page 5. Alternate serial modulation data input pin. Address bits are followed by data bits. Internal multiplexer output. Selects from oscillator frequency, main or auxiliary reference frequency, main or auxiliary divided VCO frequency, serial data out or testability signals. This pin can be tri-stated from the General Synthesizer Registers. For more information, see "General Synthesizer Registers" on page 22. Reference crystal AC ground, or external oscillator complementary input. Reference crystal input, or external oscillator differential input. Reference crystal output, or no connect. Main VCO differential input. Main VCO complimentary differential input Auxiliary VCO differential input Auxiliary VCO complimentary differential input Data Pin 27 Digital input /CS Pin 28 Digital input Mod_in Mux_out Pin 2 Pin 3 Digital input Digital output Xtalacgnd /Osc Xtalin/Osc Xtalout/NC Fvco_main /Fvco_main Fvco_aux /Fvco_aux CPout_main Pin 13 Pin 14 Pin 15 Pin 7 Pin 8 Pin 23 Pin 22 Pin 11 Ground/Input Input Input Input Input Input Input Analog Output Main charge pump output. The gain of the main charge pump phase detector can be controlled from the General Synthesizer Registers. Programmable output pin. Indicates main phase detector out-of-lock as an active low pulsing open collector output (high impedance when lock is detected), or assists the loop filter in steering the main VCO. This pin is configured from the General Synthesizer Registers. LD/PSmain Pin 9 Analog Output Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 13 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Pin Label CPout_aux Pin # Pin 20 Type Analog Output Description Auxiliary charge pump output. The gain of the auxiliary charge pump phase detector can be controlled from the General Synthesizer Registers. Programmable output pin. Indicates auxiliary phase detector out-of-lock as an active low pulsing open collector output (high impedance when lock is detected), or assists the loop filter in steering the auxiliary VCO. This pin is configured from the General Synthesizer Registers. LD/PS aux Pin 18 Analog Output VCCdigital GNDdigital VCCxtal GNDxtal VCCecl/cml GNDecl/cml VCCcp_main, VCCcp_aux Pin 26 Pin 25 Pin 16 Pin 17 Pins 6, 24 Pin 5 Pins 10, 19 Pin 26 Pin 4 Power and Ground Power and Ground Power and Ground Power and Ground Power and Ground Digital 3 Volts. Digital Ground. Crystal oscillator ECL/CML 3 Volts. Crystal Oscillator Ground. ECL/CML 3 Volt. Removing power safely powers down the associated divider chain and charge pump. ECL/CML Ground. Main and auxiliary charge pump 3 to 5 Volt. Removing power safely powers down the associated divider chain and charge pump. Main and auxiliary charge pump Ground. Substrate isolation, connect to Ground Power and Ground Power and Ground GNDcp_main, GNDcp_aux VSUBdigital Power and Ground - Note: Associated pairs of power and ground pins need to be decoupled using 0.1 F capacitors. Note: The PS1200 is supplied in an exposed pad 28-pin TSSOP package (EP-TSSOP). The exposed pad is located on the bottom side of the package, and must be connected to ground for proper operation. The exposed pad should be soldered directly to the circuit board. Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 14 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Absolute Maximum Ratings Maximum Analog Supply Voltage: Maximum Digital Supply Voltage: Maximum Charge Pump Supply Voltage: Storage Temperature: Operating Temperature: 3.6 VDC 3.6 VDC 5.25 VDC -65C to +150C -40C to +85C Recommended Operating Conditions Analog Supplies: Digital Supply: Charge Pump Supplies Operating Temperature (TA): +2.7 to +3.3 VDC +2.7 to +3.3 VDC +2.7 to +5.0 VDC -40C to +85C Electrical Characteristics Test Conditions (unless otherwise stated) Analog Supplies: Digital Supply: Charge Pump Supplies Temperature (TA): 3.0 VDC 3.0 VDC 3.0 VDC -40C to +85C . Table 2: Power Consumption Symbol Ptotal Parameter Total power consumption Conditions Charge pump currents of 200 A Both synthesizers fractional Fref_main = 20 MHz Fref_aux = 1 MHz Min. Typ. 51 Max. Units mW ICC-PWDN Power down current - 10 - A Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 15 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Table 3: Reference Oscillator Symbol Fosc Vosc Fshift_ship Parameter Reference oscillator frequency Oscillator sensitivity (as a buffer) Frequency shift at shipping Conditions AC Coupled, single-ended T = 25C, Vxtal = 3.0 V With 1% tolerance 20 pF crystal loading capacitors -40C < T < +85C Vxtal = 3.0 V T = 25C 2.7 V Vxtal 3.3 V Min. 0.05 Typ. Max. 50 2.0 3 Units MHz Vpp ppm Fshift_temp Fshift_supply Frequency shift vs temperature Frequency shift vs supply voltage - - 3 0.3 Table 4: VCOs Symbol Fvco_main Fvco_aux Vvco Zvco_in Fstep_main Fstep_aux Parameter Main synthesizer operating frequency Auxiliary synthesizer operating frequency RF input sensitivity RF input impedance Main Fractional-N tuning step size Aux Fractional-N tuning step size AC Coupled Conditions Sinusoidal Min. 800 Typ. Max. 6500 Units MHz 400 50 - 1000 1200 250 mVpeak Hz F ref_main / 216 or Fref_main / 28 Fref_aux / 210 Table 5: Noise Symbol Pnf PIB Parameter Phase noise floor Total spurious power Conditions In PLL loop bandwidth Min. Typ. -132 + 20Log(N) -70 Max. Units dBc/Hz dBc Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 16 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Table 6: Phase Detectors and Charge Pumps Symbol Fref_main Fref_aux Icp-source Icp-sink Icp-accuracy Icp vs. Vcp Icp vs. T Icp vs. Vcp Parameter Main phase detector frequency Auxiliary phase detector frequency Charge pump output source current Charge pump output sink current Charge pump output voltage linearity range Charge pump current vs. temperature Charge pump current vs. voltage 0.5V VCP (VCCcp - 0.5V) T = 25C VCP = 0.5VCCcp -40C < T < +85C 0.5V VCP (VCCcp - 0.5V) T = 25C VCP = 0.5VCCcp 125 -125 Gnd + 400 +/- 20 1000 -1000 VCCcp 400 5 8 % mV % A Conditions Min. Typ. Max. 25 Units MHz Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 17 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Table 7: Digital Pins Symbol VIH VIL VOH VOL Parameter High level input voltage Low level input voltage High level output voltage Low level output voltage Conditions IOH = -2 mA IOL = 2 mA Min. 0.7Vdigital Vdigital 0.2 Typ. Max. 0.3V digital Gnd + 0.2 Units V Timing Table 8: Timing -- Serial Interface Symbol fclock tsu thold Parameter Clock frequency Data and /CS set up time to Clock rising Data and /CS hold time after Clock rising Conditions Min. 3 0 Typ. Max. 100 Units MHz ns ns Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 18 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Registers This section describes the PS6500's registers. All register writes are programmed address first, followed directly with data. MSBs are entered first. On power up, all register are reset to zero. Register Map Table 9: PS6500 Register Map Address H0 H1 H2 H3 H4 H5 H6 H7 H8 H9 Registera Length (with address bits) 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 2 length 12 bits Main divider register Main dividend MSB register Main dividend LSB register Aux divider register Aux dividend register Reference frequency dividers register Control register - Phase detector/Charge pumps Control register - Power down/Multiplexer Output select Modulation control register Modulation data register Modulation data registerb - direct input a. b. All registers are write-only. No address bits are required for modulation data. Any serial data between 2 and 12 bits long is considered modulation data. Register Descriptions For more information on register loading order, see "Register Loading Order" on page 10. Main Synthesizer Registers Figure 4: Hex0 Main Divider Register (Write only) A3 A2 A1 A0 11 0 0 0 0 X 10 9 X X 8 7 6 5 4 3 2 1 0 Main Synthesizer Divider index Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 19 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer This register contains the integer portion divided by four closest to the desired fractional-N (or the integer-N) value minus 32 for the main synthesizer. This register, in conjunction with the main dividend registers (which controls the fraction offset from -0.5 to +0.5), permits selection of a precise frequency. Note: The fixed divide-by-four divider upstream from the programmable main divider must be taken into consideration when determining the value to be programmed in this register. Refer to "Synthesizer Register Programming" on page 6 for more details Values to be loaded are: * Main Synthesizer Divider Index = 9-bit value for the integer portion of the main synthesizer dividers. Valid values for this register are from 6 to 505 (fractional-N) or from 0 to 511 (integer-N). Figure 5: Hex1 Main Dividend MSB Register (Write only) A3 A2 A1 A0 11 0 0 0 1 X 10 9 X 8 7 6 5 4 3 2 1 0 Main Synthesizer Dividend (MSBs) Figure 6: Hex2 Main Dividend LSB Register (Write only) A3 A2 A1 A0 11 0 0 1 0 X 10 9 X X 8 X 7 6 5 4 3 2 1 0 Main Synthesizer Dividend (LSBs) These registers control the fraction part of the desired fractional-N value and permit an offset of - 0.5 to + 0.5 to the main integer selected through the Main Divider Register. Values to be loaded are: * Main Synthesizer Dividend (MSBs) = 10-bit value for the MSBs of the 18-bit dividend for the main synthesizer. * Main Synthesizer Dividend (LSBs) = 8-bit value for the LSBs of the 18-bit dividend for the main synthesizer. Note: When in 10-bit mode, the Main Synthesizer Dividend (LSBs) is not required. For information on programming these registers, see "Synthesizer Register Programming" on page 6. For information on loading order for these registers, see "Register Loading Order" on page 10. Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 20 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Auxiliary Synthesizer Registers Figure 7: Hex3 Auxiliary Divider Register (Write only) A3 A2 A1 A0 11 0 0 1 1 X 10 9 X X 8 7 6 5 4 3 2 1 0 Auxiliary Synthesizer Divider Index This register contains the integer portion closest to the desired fractional-N (or integer-N) value minus 32 for the auxiliary synthesizer. This register, in conjunction with the auxiliary dividend register, which controls the fraction offset (from - 0.5 to + 0.5) permits selection of a precise frequency. Values to be loaded are: * Auxiliary Synthesizer Divider Index = 9-bit value for the integer portion of the auxiliary synthesizer dividers. Valid values for this register are from 6 to 505 (fractional-N) or from 0 to 511 (integer-N). Figure 8: Hex4 Auxiliary Dividend Register (Write only) A3 A2 A1 A0 11 0 1 0 0 X 10 9 X 8 7 6 5 4 3 2 1 0 Auxiliary Synthesizer Dividend This register controls the fraction part of the desired fractional-N value and permits an offset of - 0.5 to + 0.5 to the auxiliary integer selected through the Auxiliary Divider Register. Values to be loaded are: * Auxiliary Synthesizer Dividend = 10-bit value for the dividend for the auxiliary synthesizer. For information on programming these registers, see "Synthesizer Register Programming" on page 6. For information on loading order for these registers, see "Register Loading Order" on page 10. Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 21 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer General Synthesizer Registers Figure 9: Hex5 Reference Frequency Dividers Register (Write only) A3 A2 A1 A0 11 0 1 0 1 X 10 9 X 8 7 6 5 4 3 2 1 0 Main Reference Frequency Divider Index Auxiliary Reference Frequency Divider Index This register configures the dual-programmable reference frequency dividers for the main and auxiliary synthesizers. The dual-programmable reference frequency dividers provide the reference frequencies to the phase detectors by dividing the crystal oscillator frequency. The lower five bits hold the reference frequency divide index for the main phase detector. The next five bits hold the reference frequency divide index for the auxiliary phase detector. Divide ratios from 1 to 32 are possible for each reference frequency divider. Values to be loaded are: * Main Reference Frequency Divider Index = Desired main oscillator frequency division ratio - 1. Default value on power up is 0, signifying that the reference frequency is not divided for the main phase detector. * Auxiliary Reference Frequency Divider Index = Desired Auxiliary oscillator frequency division ratio - 1. Default value on power up is 0, signifying that the reference frequency is not divided for the auxiliary phase detector. Figure 10: Hex6 Phase Detectors Register (Write only) A3 A2 A1 A0 11 0 1 1 0 10 9 8 7 6 5 4 3 2 1 0 Main Phase Detector Gain Main Power Steering/Lock Detect Enable Auxiliary Phase Detector Gain Auxiliary Power Steering/Lock Detect Enable This register permits control of the gain for both phase detectors, and configuration of the LD/PS pins for frequency power steering or lock detection. Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 22 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Values to be loaded are: * Main Phase Detector Gain = 5-bit value for programmable main phase detector gain, Kd, of 20 to 160 A/radian in steps of approximately 5 A/radian. Valid range is from 4 to 31 decimal for 20 to 160 A/radian respectively. * Main Power Steering Enable = 1-bit value to enable the frequency power steering circuitry of the main phase detector. When this bit is a 0, the LD/PSmain is configured to be a lock detect active low open collector pin. When this bit is a 1, the LD/PSmain is configured to be a frequency power steering pin and can be used to bypass the external main loop filter to provide faster frequency acquisition. * Aux Phase Detector Gain = 5-bit value for programmable auxiliary phase detector gain, Kd, of 20 to 160 A/radian in steps of approximately 5 A/radian. Valid range is from 4 to 31 decimal for 20 to 160 A/radian respectively. * Aux Power Steering Enable = 1-bit value to enable the frequency power steering circuitry of the auxiliary phase detector. When this bit is a 0, the LD/PSaux is configured to be a lock detect active low open collector pin. When this bit is a 1, the LD/PSaux is configured to be a frequency power steering pin and may be used to bypass the external auxiliary loop filter to provide faster frequency acquisition. Figure 11: Hex7 Power Down and Multiplexer Output Register (Write only) A3 A2 A1 A0 11 0 1 1 1 X 10 9 X 8 7 6 5 4 3 2 1 0 Full Power Down Main Synthesizer Power Down Main Synthesizer Mode Main Synthesizer Fractionality Auxiliary Synthesizer Power Down Auxiliary Synthesizer Mode Multiplexer Output Selection Mux_out Pin Tri-State Enable This register permits control of the power-down modes, internal multiplexer output and Main synthesizer fractionality. Values to be loaded are: * Full Power Down = 1-bit value for powering down the whole chip except for the reference oscillator and the serial interface. When this bit is 0, the PS6500 is powered up. When this bit is 1, the PS6500 is in full power-down mode excluding the Mux_out pin. Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 23 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer * Main Synthesizer Power Down = 1-bit value for powering down the main synthesizer. When this bit is 0, the main synthesizer is powered up. When this bit is 1, the main synthesizer is in power down mode. * Main Synthesizer Mode = 1-bit value for powering down the main synthesizer's modulator and fractional unit to operate as a integer-N synthesizer. When this bit is 0, the main synthesizer is in fractional-N mode. When this bit is 1, the main synthesizer is in integer-N mode. * Main Synthesizer Fractionality = 1-bit value to configure the size of the main modulator. This has a direct effect on power consumption and on the level of fractionality and step size. When this bit is 0, the main modulator is 18-bit with fractionality of 218 and step size of Fref_main/262144. When this bit is 1, the main modulator is 10-bit with fractionality of 210 and step size of Fref_main/1024. * Auxiliary Synthesizer Power Down = 1-bit value for powering down the auxiliary synthesizer. When this bit is 0, the auxiliary synthesizer is powered up. When this bit is 1, the auxiliary synthesizer is in power-down mode. * Auxiliary Synthesizer Mode = 1-bit value for powering down the auxiliary synthesizer's modulator and fractional unit to operate as a integer-N synthesizer. When this bit is 0, the auxiliary synthesizer is in fractional-N mode. When this bit is 1, the auxiliary synthesizer is in integer-N mode. Note: There are no special power up sequences required for the PS6500. * Multiplexer Output Selection = 3-bit value for selecting which internal signal is output to the Mux_out pin. Internal signals available on this pin are: -- Reference Oscillator: Fref -- Main or auxiliary divided reference (post reference frequency main or auxiliary dividers): Fref_main or Fref_aux -- Main or auxiliary phase detector frequency (post main and auxiliary frequency dividers): Fpd_main or Fpd_aux -- Serial data out, for loop-back and test purposes Refer to the following table for more information. Table 10: Multiplexer Output Multiplexer Output Select bit 2 0 0 0 0 1 1 1 Multiplexer Output Select bit 1 0 0 1 1 0 0 1 Multiplexer Output Select bit 0 0 1 0 1 0 1 0 Multiplexer Output (Mux_out) Reference Oscillator Auxiliary Reference Frequency (Fref_aux) Main Reference Frequency (Fref_main) Auxiliary Phase Detector Frequency (Fpd_aux ) Main Phase Detector Frequency (Fpd_main ) Serial Data Out Serial Interface Register Test Output Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 24 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer * Mux_out Pin Tri-State Enable = 1-bit value for tri-stating the Mux_out pin. When this bit is 0, the Mux_out pin is enabled. When this bit is 1, the Mux_out pin is tri-stated. Figure 12: Hex8 Modulation Control Register (Write only) A3 A2 A1 A0 11 10 1 0 0 0 X X 9 8 7 6 5 4 3 0 2 0 1 0 0 0 Reserved Bits Modulation Data Magnitude Offset Modulation Data Input Select Modulation Address Disable This register is used to configure the modulation unit of the main synthesizer. The modulation unit provides for adding or subtracting a frequency offset to the selected center frequency at which the main synthesizer is operating. The size of the modulation data sample, controlled by the duration of /CS, can be from 2 to 12 bits wide, to provide from 4 to 4096 selectable frequency offsets steps. The modulation data magnitude offset selects the magnitude multiplier for the modulation data and can be from 0 to 8. Values to be loaded are: Modulation Data Magnitude Offset = 4-bit value indicating magnitude multiplier (m) for the modulation data samples. Valid values range from 0 to 13, effectively providing a 2m multiplication of the modulation data sample. Modulation Data Input Select = 1-bit value indicating the pin on which modulation data samples are serially input when /CS is between 2 and 12 bits long. When this bit is 0, modulation data samples are to be presented on the Data pin. When this bit is 1, modulation data samples are to be presented on the Mod_in pin. For more details, please refer to section "Direct Digital Modulation" on page 10. Modulation Address Disable = 1-bit value indicating the presence of the address as modulation data samples are presented on either the Mod_in or Data pins. When this bit is 0, address is presented with the modulation data samples (i.e. all transfers are 16 bits long). When this bit is 1, no address is presented with the modulation data samples (i.e. all transfers are 2 to 12 bits long). For more details, please refer to section "Direct Digital Modulation" on page 10. Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 25 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Figure 13: Hex9 Modulation Data Register (Write only) A3 A2 A1 A0 11 1 0 0 1 10 9 8 7 6 5 4 3 2 1 0 Modulation Data Bits This register is used to load the modulation data samples to the modulation unit. This value is transferred to the modulation unit on the falling edge of Fpd_main where it will be passed to the main modulator at the selected magnitude offset on the next falling edge of Fpd_main. Values to be loaded are: Modulation Data Bits = Modulation data samples representing desired instantaneous frequency offset to the selected main synthesizer frequency (selected channel) before being affected by the Modulation Data Magnitude Offset. Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 26 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Packaging Information Figure 14: 28-Pin EP-TSSOP TOP VIEW b e 1 EXPOSED PAD BOTTOM VIEW P1 E1 E P D SIDE VIEW DETAIL A A1 A2 L Table 11: 28-Pin EP-TSSOP Dimensions Min A A1 A2 D E E1 L P P1 e b Max 1.10 0.05 0.85 9.70 BSC 6.40 BSC 4.30 0.50 4.50 0.70 3.5 3.0 0.65 BSC 0.19 0.30 0.15 0.95 All dimensions in millimeters (mm) Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 27 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 PS6500 6.5 GHz Fractional-N Frequency Synthesizer Ordering Information Table 12: Ordering Information Temperature Range Minimum Order Quantity 2 Part Number PS6500AIT-ES2/2 Package 28-Pin TSSOP Notes Engineering prototype units that are not necessarily representative of the final device's electrical specifications. Verified for functionality only, quality and reliability verification not completed. PS6500AIT -40 to 85C 28-Pin TSSOP 50 Electrostatic Discharge Information The PS6500 device is an electrostatic sensitive device. Observe precautions when handling. Philsar Semiconductor Inc. 146 Colonnade Road S. Nepean, Ontario, Canada K2E 7Y1 - 28 - Tel: 613-274-0922 Fax: 613-274-0915 www.philsar.com PMP-001-DS3 V1.1 |
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